spt7810 10-bit, 20 msps, ecl output a/d converter features ? monolithic 20 msps converter ? on-chip track/hold ? bipolar 2.0 v analog input ? 60 db snr @ 1 mhz input ? low power (1.3 w typical) ? 5 pf input capacitance ? ecl outputs applications ? medical imaging ? professional video ? radar receivers ? instrumentation ? electronic warfare ? digital communications signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 analog prescaler 10 digital output successive interpolation stage i successive interpolation stage i+1 successive interpolation stage n analog input 4 coarse a/d t/h amplifier bank aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa decoding network general description the spt7810 a/d converter is a 10-bit monolithic converter capable of word rates of a minimum of 20 msps. on board track/hold function assures excellent dynamic performance without the need for external components. drive require- ment problems are minimized with an input capacitance of only 5 pf. inputs and outputs are ecl to provide a higher level of noise immunity in high speed system applications. an overrange output signal is provided to indicate overflow conditions. output data format is straight binary. power dissipation is very low at only 1.3 watts with power supply voltages of +5.0 and -5.2 volts. the spt7810 also provides a wide input voltage swing of 2.0 volts. the spt7810 is available in a 28-lead ceramic sidebrazed dip, pdip, and die form. commercial and industrial tempera- ture ranges are currently offered. contact the factory for availability of military temperature range and /883 processed units. block diagram
spt 2 3/11/97 spt7810 electrical specifications t a =t min - t max , v cc =+5.0 v, v ee =-5.2 v, v in = 2.0 v, v sb =-2.0 v, v st =+2.0 v, f clock =20 mhz, 50% clock duty cycle, unless otherwise specified. test test spt7810a spt7810b parameters conditions level min typ max min typ max units resolution 10 10 bits dc accuracy (+25 c) full scale integral nonlinearity 250 khz sample rate v 1.0 1.5 lsb differential nonlinearity v 0.5 0.75 lsb no missing codes vi guaranteed guaranteed analog input input voltage range vi 2.0 2.0 v input bias current v in =0 v vi 30 60 30 60 m a input resistance vi 100 300 100 300 k w input capacitance v 5 5 pf input bandwidth 3 db small signal v 120 120 mhz +fs error v 2.0 2.0 lsb -fs error v 2.0 2.0 lsb reference input reference ladder resistance vi 500 800 500 800 w reference ladder tempco v 0.8 0.8 w / c timing characteristics maximum conversion rate vi 20 20 mhz overvoltage recovery time v 20 20 ns pipeline delay (latency) iv 1 1 clock cycle output delay t a =+25 cv5 5ns aperture delay time t a =+25 cv1 1ns aperture jitter time t a =+25 c v 5 5 ps-rms dynamic performance effective number of bits f in =1 mhz 9.2 8.7 bits f in =3.58 mhz 8.8 8.3 bits f in =10.3 mhz 7.5 7.0 bits absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. supply voltages v cc ............................................................... -0.3 to +6 v v ee ............................................................... +0.3 to -6 v input voltages analog input ............................................... v fb v in v ft v ft , v fb . ................................................... +3.0 v, -3.0 v reference ladder current ..................................... 12 ma output digital outputs .......................................... +30 to -30 ma temperature operating temperature .............................. -25 to +85 c junction temperature (1) .............................................. 175 c lead temperature, (soldering 10 seconds) .......... 300 c storage temperature ................................ -65 to +150 c typical thermal impedances: 28l sidebrazed dip. q ja = 50 c/w, 28l plastic dip q ja = 50 c/w.
spt 3 3/11/97 spt7810 electrical specifications t a =t min - t max , v cc =+5.0 v, v ee =-5.2 v, v in = 2.0 v, v sb =-2.0 v, v st =+2.0 v, f clk =20 mhz, 50% clock duty cycle, unless otherwise specified. test test spt7810a spt7810b parameters conditions level min typ max min typ max units dynamic performance signal-to-noise ratio (without harmonics) f in =1 mhz +25 c i 57 60 54 57 db iv 55 58 52 55 db f in =3.58 mhz +25 c i 56 58 53 55 db iv 54 56 51 53 db f in =10.3 mhz +25 c i 50 53 47 49 db iv 47 50 44 46 db harmonic distortion f in =1 mhz +25 c i 57 60 54 57 db iv 54 57 51 54 db f in =3.58 mhz +25 c i 56 58 53 55 db iv 53 55 50 52 db f in =10.3 mhz +25 c i 46 48 43 45 db iv 45 47 42 44 db signal-to-noise and distortion f in =1 mhz +25 c i 55 57 52 54 db iv 52 49 db f in =3.58 mhz +25 c i 54 55 51 52 db iv 51 48 db f in =10.3 mhz +25 c i 44 47 41 44 db iv 43 40 db spurious free dynamic range +25 c, f in =1 mhz v 67 67 db differential phase +25 c, f in =3.58 & 4.35 mhz v 0.2 0.2 degree differential gain +25 c, f in =3.58 & 4.35 mhz v 0.5 0.7 % digital inputs logic 1 voltage vi -1.1 -1.1 v logic 0 voltage vi -1.5 -1.5 v maximum input current low vi -500 200 +750 -500 200 +750 m a maximum input current high vi -500 300 +750 -500 +300 +750 m a pulse width low (clk) iv 20 20 ns pulse width high (clk) iv 20 300 20 300 ns digital outputs logic 1 voltage 50 w to -2 v vi -1.1 -0.8 -1.1 -0.8 v logic 0 voltage 50 w to -2 v vi -1.8 -1.5 -1.8 -1.5 v power supply requirements voltages v cc iv +4.75 -5.0 +5.25 +4.75 +5.0 +5.25 v -v ee iv -4.95 -5.2 -5.45 -4.95 -5.2 -5.45 v currents i cc vi 140 170 140 190 ma -i ee vi 115 140 115 160 ma power dissipation outputs open vi 1.3 1.6 1.3 1.8 w power supply rejection ratio (5 v 0.25 v, -5.2 v 2.0 v) v 1.0 1.0 lsb
spt 4 3/11/97 spt7810 figure 1a: timing diagram t pwl t pwh a a a a a a a aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa a a a a a a aa aa aa a a a data valid n+1 a a n n+1 n+2 data valid n clk output data clk t d figure 1b: single event clock aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa data valid clk output data a a a a a a clk t d table i - timing parameters parameters description min typ max units t d clk to data valid prop delay - 5 ns t pwh clk high pulse width 20 - 300 ns t pwl clk low pulse width 20 - - ns test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi
spt 5 3/11/97 spt7810 specification definitions aperture delay aperture delay represents the point in time, relative to the rising edge of the clock input, that the analog input is sampled. aperture jitter the variations in aperture delay for successive samples. differential gain (dg) a signal consisting of a sine wave superimposed on various dc levels is applied to the input. differential gain is the maximum variation in the sampled sine wave amplitudes at these dc levels. differential phase (dp) a signal consisting of a sine wave superimposed on various dc levels that is applied to the input. differential phase is the variation in the sampled sine wave phases at these dc levels. effective number of bits (enob) sinad = 6.02n + 1.76, where n is equal to the effective number of bits. n = sinad - 1.76 6.02 full-scale error (gain error) difference between measured full scale response [(+fs) - (-fs)] and the theoretical response (+4 v -2 lsbs) where the +fs (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -fs input voltage is defined as the output transition between 0-00 and 0-01. input bandwidth small signal (50 mv) bandwidth (3 db) of analog input stage. differential nonlinearity (dnl) error in the width of each code from its theoretical value. (theoretical = v fs /2 n ) integral nonlinearity (inl) linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -fs through +fs. the deviation is measured from the edge of each particular code to the true straight line. output delay time between the clock's triggering edge and output data valid. overvoltage recovery time the time required for the adc to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. signal-to-noise ratio (snr) the ratio of the fundamental sinusoid power to the total noise power. harmonics are excluded. signal-to-noise and distortion (sinad) the ratio of the fundamental sinusoid power to the total noise and distortion power. total harmonic distortion (thd) the ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. spurious free dynamic range (sfdr) the ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal.
spt 6 3/11/97 spt7810 typical performance characteristics input frequency (mhz) signal-to-noise ratio (db) snr vs input frequency 10 0 10 1 10 2 fs = 20 msps 30 40 50 60 70 20 80 a a a a a a a a 20 30 40 50 60 70 80 10 0 10 1 10 2 snr, thd, sinad vs sample rate sample rate (msps) snr, thd, sinad (db) snr, thd f in = 1 mhz sinad snr, thd, sinad vs temperature temperature (?) snr, thd, sinad (db) 45 50 55 60 65 40 f s = 20 msps f in = 1 mhz sinad snr -25 0 +25 +50 +75 snr thd thd signal-to-noise and distortion (db) 20 30 40 50 60 70 80 10 0 10 1 10 2 sinad vs input frequency input frequency (mhz) fs =20 msps 20 30 40 50 60 70 80 10 0 10 1 10 2 thd vs input frequency input frequency (mhz) total harmonic distortion (db) fs = 20 msps -120 -90 -60 -30 0 input frequency (mhz) amplitude (db) spectral response 0 1234567 8910 f s = 20 msps f in = 1 mhz
spt 7 3/11/97 spt7810 typical interface circuit the spt7810 requires few external components to achieve the stated operation and performance. figure 2 shows the typical interface requirements when using the spt7810 in normal circuit operation. the following section provides a description of the pin func- tions and outlines critical performance criteria to consider for achieving the optimal device performance. power supplies and grounding the spt7810 requires the use of two supply voltages, v ee and v cc . both supplies should be treated as analog supply sources. this means the v ee and v cc ground returns of the device should both be connected to the analog ground plane. all other -5.2 v requirements of the external digital logic circuit should be connected to the digital ground plane. each power supply pin should be bypassed as closely as possible to the device with .01 m f and 10 m f capacitors as shown in figure 2. the two grounds available on the spt7810 are agnd and dgnd. dgnd is used only for ecl outputs and is to be referenced to the output pulldown voltage. these grounds are not tied together internal to the device. the use of ground planes is recommended to achieve the best performance of the spt7810. the agnd and the dgnd ground planes should be separated from each other and only connected together at the device through an inductance. doing this will minimize the ground noise pickup. voltage reference the spt7810 requires the use of two voltage references: v ft and v fb . v ft is the force for the top of the voltage reference ladder (+2.5 v typ), v fb (-2.5 v typ) is the force for the bottom of the voltage reference ladder. both voltages are applied across an internal reference ladder resistance of 800 ohms. in addition, there are 3 reference ladder taps (v st ,v rm and v sb ). v st is the sense for the top of the reference ladder (+2.0 v), v rm is the midpoint of the ladder (0.0 v typ) and v sb is the sense for the bottom of the reference ladder (-2.0 v). the voltages seen at v st and v sb are the true full scale input voltages of the device when v ft and v fb are driven to the recommended voltages (+2.5 v and -2.5 v typical respectively). these points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. when not being used, a decoupling capacitor of .01 uf connected to agnd from each tap is recommended to minimize high frequency noise injection. an example of a reference driver circuit recommended is shown in figure 2. ic1 is ref-03, the +2.5 v reference with a figure 2 - typical interface circuit vin2 vee 8 vrm .01 f 10 f r 2r 2r 2r 2r r 4 coarse a/d 11 x 50 w d0 (lsb) d1 d2 d3 d4 d5 d6 d7 d8 d9 (msb) d10 (overrange) dg dg ag ag vcc vcc vee -2 v -5.2 v +5 v agnd ( 5 v rtn & -5.2 v rtn ) dgnd ( -2 v rtn ) vft vfb successive interpolation stage # n successive interpolation stage # i t/h amplifier bank analog prescaler vin1 10 f .01 f + 10 f .01 f 10 f .01 f + + l a a a a a a aa .01 f 1 - + 2 3 4 6 7 2 vin vout tr i m gnd r1 10 k w r2 * 30 k w r4 10 k w r3 * 30 k w ic1 ic2 (ref-03) 6 5 4 (op-07) -5.2 v .01 f +2.5 v -5.2 v +5 v .01 f vst .01 f vsb *r2 and r3 matched to 0.1% .01 f + 10 h +5 v 2 clk clk clk-in clk-in decoding network analog input analog input + 10 f +5 v .01 f + 10 f -2.5 v d2 digital outputs d1 note: d1=d2=1n5817 or equivalent. (used to prevent damage caused by power sequencing.)
spt 8 3/11/97 spt7810 tolerance of 0.6% or 0.015 v. the potentiometer r1 is 10 k w and supports a minimum adjustable range of up to 150 mv. ic2 is recommended to be an op-07 or equivalent device. r2 and r3 must be matched to within 0.1% with good tc tracking to maintain a 0.3 lsb matching between v ft and v fb . if 0.1% matching is not met, then potentiometer r4 can be used to adjust the v fb voltage to the desired level. r1 and r4 should be adjusted such that v st and v sb are exactly +2.0 v and -2.0v respectively. the analog input range will scale proportionally with respect to the reference voltage if a different input range is required. the maximum scaling factor for device operation is 20% of the recommended reference voltages of v ft and v fb . how- ever, because the device is laser trimmed to optimize perfor- mance with 2.5 v references, the accuracy of the device will degrade if operated beyond a 2% range. the following errors are defined: +fs error = top of ladder offset voltage = d (+fs -v st +1 lsb) -fs error = bottom of ladder offset voltage = d (-fs -v sb -1 lsb) where the +fs (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -fs input voltage is defined as the output transition between 0-00 and 0-01. analog input v in1 and v in2 are the analog inputs. both inputs are tied to the same point internally. either one may be used as an analog input sense and the other for an input force." the inputs can also be tied together and driven from the same source. the full scale input range will be 80% of the reference voltage or 2 volts with v fb =-2.5 v and v ft =+2.5 v. the drive requirements for the analog inputs are minimal when compared to conventional flash converters due the spt7810s extremely low input capacitance of only 5 pf and very high input resistance of 300 k w . for example, for an input signal of 2 v p-p with an input frequency of 10 mhz, the peak output current required for the driving circuit is only 628 m a. clock input the clock inputs (clk, c lk ) are designed to be driven differentially with ecl levels. the clock may be driven single ended since c lk is internally biased to -1.3 v. c lk may be left open, but a .01 m f bypass capacitor to agnd is recom- mended. as with all high speed circuits, proper terminations are required to avoid signal reflections and possible ringing that can cause the device to trigger at an unwanted time. the clk pulse width (tpwh) must be kept between 10 ns and 300 ns to ensure proper operation of the internal track-and-hold amplifier. (see timing diagram.) when operating the spt7810 at sampling rates above 3 msps, it is recommended that the clock input duty cycle be kept at 50% to optimize performance. the analog input signal is latched on the rising edge of the clk. digital outputs the format of the output data (d0-d9) is straight binary. these outputs are ecl with the output circuit shown in figure 4. the outputs are latched on the rising edge of clk with a propagation delay of 4 ns. there is a one clock cycle latency between clk and the valid output data (see timing diagram). these digital outputs can drive 50 ohms to ecl levels when pulled down to -2 v. the total specified power dissipation of the device does not include the power used by these loads. the additional power used by these loads can vary between 10 and 300 mw typically (including the overrange load) depending on the output codes. if lower power levels are desired, the output loads can be reduced, but careful consideration to the capacitive loads in relation to the oper- ating frequency must be considered. table ii - output data information analog input overrange output code d1o d9-do >+2.0 v + 1/2 lsb 1 11 1111 1111 +2.0 v -1 lsb o 11 1111 111? 0.0 v o ?? ???? ???? -2.0 v +1 lsb o oo oooo ooo? <-2.0 v o oo oooo oooo (? indicates the flickering bit between logic 0 and 1). figure 3 - output circuit data out agnd dgnd overrange output the overrange output (d10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 lsb. when this condition occurs, d10 will switch to logic 1. all other data outputs (d0 to d9) will remain at logic 1 as long as d10 remains at logic 1. this feature makes it possible to include the spt7810 into higher resolution systems. evaluation board the eb7810 evaluation board is available to aid designers in demonstrating the full performance of the spt7810. this board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. an application note describing the operation of this board as well as information on the testing of the spt7810 is also available. contact the factory for price and availability.
spt 9 3/11/97 spt7810 package outline 28-lead sidebrazed inches millimeters symbol min max min max a 0.077 0.093 1.96 2.36 b 0.016 0.020 0.41 0.51 c 0.095 0.105 2.41 2.67 d .050 typ 0.00 1.27 e 0.040 0.060 1.02 1.52 f 0.215 0.235 5.46 5.97 g 1.388 1.412 35.26 35.86 h 0.585 0.605 14.86 15.37 i 0.009 0.012 0.23 0.30 j 0.600 0.620 15.24 15.75 a b c d e f g 1 28 i h j a b c d e 1 28 j k f g h i inches millimeters symbol min max min max a 0.200 5.08 b 0.120 0.135 3.05 3.43 c 0.020 0.51 d 0.100 2.54 e 0.067 1.70 f 0.013 0.33 g 0.170 0.180 4.32 4.57 h 0.622 15.80 i 0.555 14.10 j 1.460 37.08 k 0.085 2.16 28-lead plastic dip
spt 10 3/11/97 spt7810 pin assignments ordering information part number temperature range package type spt7810aij -25 to +85 c 28l sidebrazed dip SPT7810BIJ -25 to +85 c 28l sidebrazed dip spt7810acn 0 to +70 c 28l plastic dip spt7810bcn 0 to +70 c 28l plastic dip spt7810bcu +25 c die* *please see the die specification for guaranteed electrical performance. pin functions name function dgnd digital ground d0-d9 ecl outputs (d0=lsb) d10 ecl output overrange clk clock input clk inverted clock input v ee -5.2 v supply agnd analog ground v cc +5.0 v supply v in1 , v in2 inputs (tied together at the die) v ft force for top of reference ladder v st sense for top of reference ladder v fb force for bottom of reference ladder v sb sense for bottom of reference ladder v rm middle of reference ladder clk v agnd v v v v v v v v v agnd v dgnd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 dgnd clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ft cc ee in1 in2 ee cc fb sb rm st sidebrazed and pdip signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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